Design and Fabrication of a Low-Noise CMOS Charge Sensitive Amplifier

A new design of low-noise low-power consumption charge sensitive amplifier is presented. Simulated by EDA software Cadence, the results obtained are satisfied. The DC open-loop gain is 82.9 dB with a 28 kHz -3 dB bandwidth and its phase margin is 46.9°. The maximum output noise spectral density is 1.5 μV/Hz2 at very low frequency. Using standard 3mm P-Well CMOS technology, the proposed amplifier is fabricated, and the measurement results are closed to the simulation.