Chen Xinkun, Zhou Dong, Yu Jingdong. Design and FPGA Implementation of Manchester Encoder[J]. Journal of University of Electronic Science and Technology of China, 2003, 32(3): 324-327.
Citation:
Chen Xinkun, Zhou Dong, Yu Jingdong. Design and FPGA Implementation of Manchester Encoder[J]. Journal of University of Electronic Science and Technology of China, 2003, 32(3): 324-327.
Chen Xinkun, Zhou Dong, Yu Jingdong. Design and FPGA Implementation of Manchester Encoder[J]. Journal of University of Electronic Science and Technology of China, 2003, 32(3): 324-327.
Citation:
Chen Xinkun, Zhou Dong, Yu Jingdong. Design and FPGA Implementation of Manchester Encoder[J]. Journal of University of Electronic Science and Technology of China, 2003, 32(3): 324-327.
Design and FPGA Implementation of Manchester Encoder
This paper presents a VHDL project of Manchester encoder with FPGA implementation and releases VHDL source code of some important modules. Using QuartusⅡ2.1 of Altera company, the project has been synthesized and fitted to device APEX20KE series with speed. The result of timing simulation is accord with theory. And the timing analysis shows the data rate can be up to 22.5 Mbps.
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