A New Iterative Implementation and Architecture for LOG-MAP Algorithm

This paper analyzes the parallel mechanism of logarithmic maximum a posteriori algorithm and presents a modified iterative procedure by the use of the possibility of receiving the full N-symbols frame and the symmtry being inherent in the forward-backward iteration. The procedure achieves a double decoding speed faster than that of the conventional one without the increase of RAM cost because the number of iterations is limited to a half of the code-length N. Also according to the modified algorithm this paper proposes a hardware scheme characterized by a two-busses architecture suitable for implementing with FPGA.