Choice of Best Test Sequence for VLSI Functional Testing
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Graphical Abstract
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Abstract
This paper introduces Petri net model of functional test pattern generation for VLSI. Relationships between operators involved in test sequence are accomplished via Petri. Reduced matrix compacting storage of net topology is constructed. Ambiguity of test sequence is checked via Petri net matrix. Test pattern is optimized and the best test sequence is got.
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