Wang Yong, Cheng Guangju. Analysis of Gate Delay Fault's Testability in Combinational Circuits[J]. Journal of University of Electronic Science and Technology of China, 1999, 28(1): 58-61.
Citation: Wang Yong, Cheng Guangju. Analysis of Gate Delay Fault's Testability in Combinational Circuits[J]. Journal of University of Electronic Science and Technology of China, 1999, 28(1): 58-61.

Analysis of Gate Delay Fault's Testability in Combinational Circuits

  • According to the feature of the testing for gate delay faults, the testability measures of the gate delay faults are defined (the controllability and the observability of the gate delay faults in the rising or falling transition), and the method of computing these two measures are presented, which provides the quantitative criteria of design for testability of the gate delay faults.
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