CMOS Implementation Technique of Current-mode Neural Network Classifier

The implementation of an optimum minimum error classifier based on the Hamming neural model is discussed for binary patterns in this paper by the use of current-mode technique.The CMOS implementation of current-mode winner-take all(WTA) circuit and the subnet for calculating matching scores between two patterns are demonstrated.Computer simulations are in agreement with the theory.The classifier mimics well the heavy use of lateral inhibition evident in the biological neural nets.The resulting circuits are simple and particularly suitable for integration with standard VLSI technology,thus will have perspecitve in many application areas.