基于位串行卷积神经网络加速器的运动想象脑电信号识别系统

A motor imagery EEG signal recognition system based on a Bit-Serial convolutional neural network accelerator

  • 摘要: 准确识别运动想象脑电信号是神经科学和生物医学工程领域的重要挑战。设计了基于位串行卷积神经网络加速器的脑电信号识别系统,充分利用其小体积、低能耗和高实时性的优势。从软件层面,介绍了脑电数据的预处理、特征提取及分类过程,并采用格拉姆角场转换将一维信号映射为二维特征图供网络处理。在硬件层面,提出了列暂存数据流和固定乘数原位串行乘法器等方法,在FPGA上实现了位串行卷积神经网络加速器的原型验证。实验表明,基于位串行LeNet-5加速器的FPGA实现对BCI竞赛IV数据集2a和2b的分类平均准确率分别达到95.68%和97.32%,kappa值分别为0.942和0.946,展现出的优异性为运动想象脑电信号识别的高效实现提供了思路。

     

    Abstract: Accurate recognition of motor imagery electroencephalogram (EEG) signals is a significant challenge in neuroscience and biomedical engineering. This paper presents an EEG signal recognition system based on a bit-serial convolutional neural network (CNN) accelerator, leveraging its advantages of compact size, low power consumption, and high real-time performance. On the software side, the paper systematically introduces the preprocessing, feature extraction, and classification of EEG data, utilizing Gramian Angular Field (GAF) transformation to map one-dimensional signals into two-dimensional feature maps for network processing. On the hardware side, innovative methods such as column-buffering dataflow and fixed-multiplier bit-serial multiplication are proposed, and a prototype of the bit-serial CNN accelerator is successfully implemented on FPGA. The results show that the FPGA implementation of the bit-serial LeNet-5 accelerator achieves average classification accuracies of 95.68% and 97.32% on the BCI Competition IV datasets 2a and 2b, with kappa values of 0.942 and 0.946, respectively. These performances provide an efficient solution for the recognition of motor imagery EEG signals.

     

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