Abstract: As the conversion rate increases, the sampling front-end gradually becomes a bottleneck limiting the performance of high-speed and high-resolution Analog-to-Digital Converters (ADCs). A 4GS/s 13-bit Time- Interleaved-Pipelined-Successive Approximation Register (TI-Pipelined-SAR) ADC with an integrated dual-input buffer is implemented in a 16nm FinFET process. To minimize the intra-channel kickbacks and the crosstalk between multi-channel sampling switches, a dual-input buffer structure is adopted. Additional offset mismatch and gain mismatch introduced by dual-input buffer are corrected using an inter-channel calibration algorithm. An all-CMOS fast turn-on bootstrapped sampling switch circuit is also presented to improve the sampling rate. With 500 MHz input, the ADC achieves a Spurious Free Dynamic Range (SFDR) of 74.1 dBc and a Signal-to-Noise Distortion Ratio (SNDR) of 59.6 dB.