一种巨磁阻隔离器的设计与工艺制备

Design and processing of a giant magneto-resistive isolator

  • 摘要: 为了保证信号完整且高速地传输,必须要在电子系统之间实施电气隔离。首先通过磁控溅射法制备了结构为Sub(Si/SiO2)(300 nm)/Ta(5 nm)/NiFe(4.5 nm)/CoFe(1.5 nm)/Cu(2.5 nm)/CoFe(5.5 nm)/IrMn(10 nm)/Ta(5 nm)的顶钉扎自旋阀巨磁阻薄膜,在制备薄膜的基础上,通过光刻、离子束(IBE)刻蚀、金属剥离等半导体工艺制备了一种巨磁阻隔离器,通过等离子体化学气相沉积法(PECVD)生长SiO2隔离栅的厚度为4 μm,其耐压强度可达2 kV。利用吉时利多功能探针台进行晶圆级测试,当平面线圈的输入电流为6 mA时,巨磁阻隔离器输出电压约为20 mV,对晶圆切片引线后进行电路级测试,巨磁阻隔离器工作频率为25 MHz。整个工艺流程需要6次光刻,工艺参数稳定,对于巨磁阻隔离器的制备具有参考价值。

     

    Abstract: To ensure the complete and high-speed transmission of signals, electrical isolation must be implemented between electronic systems. This paper first prepared a pinned spin valve giant magnetoresistive (GMR) thin film with the structure Sub(Si/SiO2)(300 nm)/Ta(5 nm)/NiFe(4.5 nm)/CoFe(1.5 nm)/Cu(2.5 nm)/CoFe(5.5 nm)/IrMn(10 nm)/Ta(5 nm) using magnetron sputtering. Based on the preparation of the thin film, a GMR isolator was fabricated through semiconductor processes such as photolithography, ion beam (IBE) etching, and metal stripping. A SiO2 isolation gate with a thickness of 4 μm was grown by plasma enhanced chemical vapor deposition (PECVD), which can withstand a voltage of up to 2 kV. Wafer-level testing was performed using a Keithley multifunction probe stage, and the output voltage of the giant magnetoresistive isolator was about 20 mV when the input current of the planar coil was 6 mA. Circuit-level testing was performed after slicing the wafers for leads, and the giant magnetoresistive isolator was operated at a frequency of 25 MHz. The entire process requires six photolithographic steps, and the process parameters are stable, providing reference value for the preparation of GMR isolators.

     

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