Abstract: To address the issues of area and power consumption in traditional successive approximation register analog-to-digital converters (SAR ADCs) used in column-level readout circuits of CMOS image sensors, this paper proposes a high-speed SAR ADC with a globally shared DAC, tailored for large arrays. The proposed architecture is based on the concept of sharing a core DAC across multiple columns. It extracts the largest area-consuming component of traditional column-level SAR ADCs, the capacitor array DAC, and replaces it with a globally shared DAC that utilizes different weighted DAC signals, along with a multiplexer and adder, instead of traditional column-level multiplexing techniques. This method simplifies each column-level SAR ADC to only require a comparator, a multiplexer-adder, and partial digital logic, significantly reducing the area requirements while maintaining the speed and precision advantages of SAR ADCs.　　The proposed method was designed and simulated using a 55nm 1P4M CMOS process. With an analog voltage of 3.3V, a digital voltage of 1.2V, a clock frequency of 120MHz, and an input signal range of 1.6V, the 12-bit SAR ADC designed in this work achieves a static differential nonlinearity (DNL) of -0.8/0.8 LSB, an integral nonlinearity (INL) of -1.4/0.4 LSB, a signal-to-noise ratio (SNR) of 68.24 dB, and an effective number of bits (ENOB) of 11.02 bits. The total area is 10μm * 350μm, with a power consumption of 264.0μW. Compared to existing SAR ADCs, this design reduces the area requirements significantly while maintaining high speed and precision, providing theoretical support for the application of SAR ADCs in the column-level readout circuits of high-speed CMOS image sensors.