Abstract: Polar code proposed based on channel polarization is the only one that is proven to achieve the Shannon limit. The mainstream successive cancellation list (SCL) decoding algorithm shows the extremely high latency due to its massive path splitting and path metrics. To solve this problem, a low-latency SCL decoding hardware architecture based on special nodes is proposed in this paper. Pruning or split-reducing is considered for different nodes to reduce the decoding latency and improve the throughput with slight performance degradation. Moreover, to enhance the flexibility, the prior information of different code lengths and code rates is stored in the read-only memory (ROM) and is selected based on the input configuration. The implementation results of the proposed architecture on field programmable gate array (FPGA) show that the decoding cycles are reduced by 40.32%~56.87% compared with the standard SCL decoder with the code length varying from 128 to 1024 bit and the code rate varying from 0.3 to 0.5.