Abstract: Based on the discussion of the structure of digital down-conversion (DDC) in software radio receiver, this paper suggests the classification of decimation filtering to reduce the taps of the anti-aliasing filters, and the suggestion to use different resources at separate step of decimation filtering during the multiple steps, so as to make the resources of FPGA high-efficient utilization. Besides, a new algorithm——clock-selective-computing algorithm fitting for FIR decimation filter is proposed and tested by Altera's EP2S60F484C4. Results validate that the new algorithm spends less resources.