Abstract: Delay fault testing usually requires the application of consecutive two-pattern tests, which include multiple input change (MIC) test sequences and single input change (SIC) test sequences. SIC has been designated to be more effective than MIC when high robust delay fault coverage is targeted in a series of previous theoretical and experimental results. In this paper, a novel accumulator-based BIST test pattern generator (TPG) scheme is proposed for delay fault testing. Compared with previous schemes, ours has two merits:low hardware overhead and low time overhead. As accumulators are available in many very large scale integration circuits and can be reused, the proposed scheme does not introduce much hardware overhead and performance degradation and hence can be applied effectively as built in self test (BIST) test pattern generator for robustly delay fault testing.