高效实时的抽取滤波器的FPGA实现
High Efficient and Real-Time Realization of Decimation Filter Based on FPGA
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摘要: 介绍了分布式算法实现乘积和运算的原理及工程上的实现方式,提出了适合现场可编程门阵列器件基本查找表结构的改进分布式算法,通过计算机仿真,在具体器件上实现了抽取滤波器。实验结果表明:该分布式算法结构可以充分利用现场可编程门阵列器件的资源,并且只引入固定的流水线延迟,具有很好的高效性和实时性。Abstract: This paper briefly talks about the principle of distributed arithmetic algorithm and its application to the multiply-accumulate before puts forward a improved distributed arithmetic algorithm which suits the look up table structure of filed programmable gate array well. Simulated and tested results on real device shows that high efficient and real-time decimation filter with some invariable pipeline delay can be achieved through this improved algorithm. The fabricated decimation filters are used in real digital receiver.