Abstract: o overcome the limitations imposed by comparators, sub-DACs, and residual amplifiers upon high-speed analog to digital converter (ADC) area and power design, a segmented multi-division search algorithm is proposed and a novel A/D conversion scheme is developed. This scheme can the realized the optimization of speed and power dissipation. An 8-bit 250 MHz ADC with chip area only 1.0 mm×0.8 mm is designed by using SMIC 0.35μm CMOS models. Simulation reveals that the ADC possesses 85 mW power consumption and 64.92 dB spurious free dynamic range (SFDR) under Nyquist conversion, both of its INL and DNL less than ±0.5LSB.