Abstract: Based on arithmetic additive generator, a kind of design-for-testability and test strategy for direct-form fine-grained pipelined delayed least mean square adaptive filter is presented. The design improves the circuit testability by insulating the filter building modules and converting registers into scan chains. Reuses of some adders and registers existing in circuit result in the elimination or minimization of the additional hardware overhead for test. The test strategy can detect any combinational stuck-at faults within the circuit basic building cell at-speed and without any degradation of the original circuit performance.