Abstract: In this paper, a hardware implementation scheme of the scheduling module in Optic burst switching(OBS) edge node receiver is presented. Input serial polling(ISP), which is based on virtual output queuing(VOQ) mechanism, is a kind of fair and high-performance algorithm for crossbar arbitrating. Focused on ISP, the design allows receiving, switching and Ethernet-assembling for 6 routs of 1 000M-OBS data with two high-speed FPGA chips. The 6 routs of data mentioned above are totally independent, and there exists communication between two FPGA chips.