一种LOG-MAP算法的改进迭代实现及其结构

详细信息

A New Iterative Implementation and Architecture for LOG-MAP Algorithm

摘要: 对LOG-MAP算法进行了可并发性分析,利用可以完整接收一个N长符号传输帧的条件以及正向迭代和反向迭代中的固有对称性质,提出了LOG-MAP算法的一种修正迭代实现算法,其正向和反向迭代计算次数只需码长N的一半,故比标准LOG-MAP算法提高了一倍的处理速度,且没有空间开销的增加、同时,根据修正的迭代实现算法给出了相应的适于FPGA实现的双总线硬件结构的实现方案。
- 最大后验概率 /
- 对数最大后验概率 /
- 迭代算法 /
- 双总线结构
Abstract: This paper analyzes the parallel mechanism of logarithmic maximum a posteriori algorithm and presents a modified iterative procedure by the use of the possibility of receiving the full N-symbols frame and the symmtry being inherent in the forward-backward iteration. The procedure achieves a double decoding speed faster than that of the conventional one without the increase of RAM cost because the number of iterations is limited to a half of the code-length N. Also according to the modified algorithm this paper proposes a hardware scheme characterized by a two-busses architecture suitable for implementing with FPGA.
- maximum a posteriori /
- logarithmic maximum a posteriori /
- iterative algorithm /
- two-busses architecture