Abstract: This paper aims at achieving higher fault coverage for circuits under test with less hardware overhead and time consumption. One Configuration approach of multiple scan chain is presented based on the shift-and-add property of m sequence generated by Linear Feedback Shift Register (LFSR) with maxium sequence length, it enables LFSR with shorter size to drive multiple scan chains. In order to alleviate correlation between the bit streams of LFSR, a fast design meathod is presented also based on logic stimulation. Experiment results prove the effectivness of this approach, it can be used both to internal test and external test of VLSI.