Abstract: Based on TSMC 0.18 μm RF CMOS process, a hybrid digital analog composite structure is implemented to accelerate the locking time of charge-pump phase-locked loop (CP-PLL). The composite structure mainly includes two independent units: dynamic loop bandwidth unit and preset feedback loop. Among them, the control circuits of the two units are all digital circuits, and the layout information is obtained through DC synthesis and ICC automatic layout. Through the comparative analysis under the same CP-PLL parameter environment, the locking times of three schemes including the traditional structure are compared. Under the working power supply of 1.8 V, the optimized locking time is 1.12 μs, which is 76.7% higher than that of the traditional structure; the overall phase noise keeps −103.1dBc/Hz@1MHz in the steady state, which is only 0.3% higher than that of the traditional structure. Therefore, the composite structure can effectively reduce the lock-in time of power on and frequency hopping.