基于65 nm体硅CMOS技术的DICE-DFF和TMR-DFF SEU辐射硬化方法分析

Analysis of SEU Radiation-Hardened Method About DICE-DFF and TMR-DFF Based on 65 nm Bulk CMOS Technology

  • 摘要: 基于65 nm体硅CMOS工艺,采用移位寄存器链方式对普通触发器(DFF)、2种双互锁触发器(DICE-DFF,FDICE-DFF)、普通触发器空间三模冗余(TMR-DFF)和2种普通触发器时间三模冗余(TTMR-DFF300,TTMR-DFF600)这6种结构进行单粒子翻转(SEU)性能试验评估。利用Ti、Cu、Br、I、Au和Bi这6种离子对被测电路进行轰击,试验结果表明,普通触发器单粒子翻转截面最大,约为3.5×10−8~1.7×10−7 cm2/bit;时钟间隔时间600 ps的时间三模冗余结构触发器单粒子翻转截面最小,约为5×10−11~7×10−10 cm2/bit,仅为普通触发器的0.1%左右。同时,针对6种触发器单元,从速度、面积、晶体管数量以及抗SEU性能多方面进行综合分析,为后续超大规模集成电路抗SEU设计提供了一定的指导意义。

     

    Abstract: Based on 65 nm bulk CMOS technology, six kinds of DFFs including common DFF, DICE-DFF, FDICE-DFF, TMR-DFF, TTMR-DFF300 and TTMR-DFF600 were tested and analyzed by the shift register structure. Ti, Cu, Br, I, Au, Bi were used to impact the DFFs circuit. The results show common DFF has the worst cross section, which is 3.5×10−8 cm2/bit to 1.7×10−7 cm2/bit, while TTMR-DFF600 has the best cross sectionof 5×10-11 cm2/bit to 7×10-10 cm2/bit, which is only 0.1% of common DFF’s cross section. The six DFF structures were analyzed from speed, area, number of transistors and performance of SEU-hardened. Some meaningful suggestions have been provided for the design of SEU-hardened VLSI circuits.

     

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