Abstract: A novel and efficient two-channel router using separate data and control packet channels is proposed for networks-on-chip. The new scheme is compared with the traditional signal-channel and virtual-channel routers under the same traffic conditions and constraints. The simulation results show that the proposed router performs better in terms of throughput and average delay. The gate count of the router is only 20 500, and the router area after synthesis is 0.103 mm2 under SMIC 0.13 μm CMOS process technology.