芯片动态门限静态功耗的优化技术

Optimization Techniques of Static Power Dissipation in Chip with Dynamical Threshold

  • 摘要: 提出了一种双阈值电压的动态门限静态功耗优化算法。该算法通过直接统计电路门级节点的松弛裕度,利用静态时序分析其最大松弛裕度及邻节点松弛裕度特征,区分电路中的关键与非关键节点并分步调整其相应的阈值电压,从而有效地实现了对CMOS电路静态功耗的优化设计。基于ISCA85基准实验电路集,采用该技术和以往的算法进行了对比验证。结果表明,该算法在不降低静态功耗优化效率的同时,优化时间缩短了95%以上,适合于超大规模电路静态功耗优化。

     

    Abstract: A novel dynamic threshold static power optimization algorithm is presented. After accounting the relaxation margins of gate level nodes, the maximum margin in circuits and characteristics in adjacent gates are analyzed with static timing, the key and non-key nodes are then divided, their thresholds are adjusted within stages, and the efficient power optimization of CMOS circuits is finally implemented. Compared with existing algorithms, experimental results with ISCA85 benchmark circuits show that processing time of the algorithm can be reduced 95% at lest without reducing the optimization efficiency of static power.

     

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