Abstract: In the multiple-input multiple-output (MIMO) orthogonal frequency-division multiplexing based systems, interleaver and deinterleaver with multi-mode and high-speed are required. In this paper, a novel 36-mode interleaver fully compliant to IEEE 802.11n wireless local area network (WLAN) protocol is presented. Three design techniques are proposed:merging permutations, replacing arithmetic expressions with optimized circuits, and multiplexing interleaver/deinterleaver. The proposed design is implemented in both FPGA and ASIC. It achieves a reduction of silicon area and power consumption when compared with other similar works. In SMIC 0.13 μm CMOS technology, the maximal operating frequency is synthesized 400 MHz and the corresponding power dissipation is 10.8 mW. The core size is 0.066 7 mm2.