Abstract: A novel design methodology for programmable logic cores (PLCs) is proposed. A structured hardware description strategy is applied where some repeatable tiles are created and then replicated to form the fabric of the PLC, afterwards, the semi-custom design flow is used for layout generation. Compared with the existing ‘soft' PLCs design methodlogy, the problem of ‘combinational cycle’ is solved through bypassing the process of synthesis. Experimental results show that the area of PLCs designed following this methodology is reduced by about 50%. The feasibility of this methodology is verified through the implementation of desired logic functionality on the proof-of-concept prototype chip.