Abstract: In order to implement a high performance layer 2 switch address lookup function with minimum hardware consumption, a 10-bit Hash algorithm consisting of registers and XoR gates was presented by analyzing the characteristics of switch chip address table and cyclic redundancy check algorithm. 48-bit physical address is transferred into 10-bit lookup address in parallel and the address table of 1 024 storage depth can be quickly and accurately searched. The layer 2 switch chip using this address lookup algorithm can implement line speed exchange. The performance of the network equipments using the switch chips can be improved. The generated Hash addresses are uniformly distributed in the 10-bit address space. The performance of the algorithm was further verified by using switch circuit implemented on FPGA.