Abstract: The high complexity Gaussian elimination (GE) algorithm of the systematic raptor decoding results in its high latency and low throughputs. A high efficiency parallel dimensionality-reduction decoding scheme is presented in this paper. The proposed scheme uses low complexity dimensionality-reduction algorithm to decode lost packets to replace the GE algorithm which decodes all source packets. Meanwhile, a full parallel structure for the decoding is proposed to implement the dimensionality-reduction-algorithm. At last, the decoder is implemented on Xilinx FPGA XC7K410T. The test results show that the scheme can achieve a 3.5 Gbps throughput within a 10^-2 packet loss probability, which is 80 times better than that of the GE algorithm.