Abstract: A novel pipelined ADC is designed. The key circuit design includes a switch sample/hold differential folded common source, common gate op amp, a two-bit ADC, and a two-bit DAC. Since the capacitance bottom plate sampling, the fully differential structure, and the bootstrapped switch are employed, the charge injection error of switch MOSFET and the effect of clock feed-through are eliminated; the linearity, SNR, resolution, and speed of the ADC are improved. The ADC have been simulated in 0.6 μm CMOS process with input frequency of 500 kHz, sample frequency of 5 MHz, power consumption of 70 mW, and SFDR of 65dB.