Abstract: A 16-bit 625 kS/s Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is presented. An improved sampling and hold circuit is proposed to optimize sampling linearity and noise performance. Segmented Capacitor Digital-to-Analog Converter (CDAC) is designed and hybrid capacitor switching method is adopted to reduce layout area and switching energy. Dither injection technique is used to improve ADC’s linearity. Two-stage integrating preamplifier is adopted to reduce comparator’s noise. Output offset storage and optimized circuit design techniques reduce comparator’s offset and noise induced by offset calibration. Comparator speed is also improved by circuit design. The prototype is fabricated using CMOS 0.18 μm process and occupies an active area of 1.15 mm². With 1 kHz sinusoid input, the measured differential input peak-to-peak amplitude is 8.8 V. Signal to Noise and Distortion (SINAD) and Spurious Free Dynamic Range (SFDR) are 85.9 dB and 110 dB respectively. Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) are −0.27/+0.32 LSB and −0.58/+0.53 LSB respectively with a power consumption of 4.31 mW.